The anti-windup measure helps to ensure that the integral component does not grow too much causing the controller to lock if it has been held at a control limit too long.
Anti-windup measures are only performed for an active I component of the controller. Limits for the anti-windup measure are by default the manipulated variables defined limits (yao, yau) of the controller (dyaw = 0). The parameter dyaw can be used to either increase (dyaw > 0) or decrease (dyaw < 0) the limits with regard to the control limits (yao, yau).
Therefore, the limits used for the anti-windup measure are:
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AWMAX = yao + dyaw
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AWMIN = yau - dyaw
Through displacement of the anti windup defined control limits in relation to the control limits (in particular with very noisy signals), the manipulated variable y can be stopped from repeatedly 'jumping away' from the control limit (D component effect to disturbances) and subsequently returning to the limiting position (I component effect with system deviation xd ≠ 0).
If the control limits are to be simultaneously effective for the anti-windup measure and the manipulated variable Y, select the parameter dyaw = 0.
By utilizing negative dyaw values, anti-windup limits can be kept smaller than control limits (useful for anti-windup halt).
Anti-Windup Reset (input status bit 13= 0)
This anti-windup measure disregards the D component, to avoid the capping of the D component peaks through the anti-windup measure. The anti-windup-reset measure corrects the I component such that: AWMIN ≤ YP + Z + YI ≤ AWMAX.
Anti-Windup Halt (input status bit 13= 1)
This anti-windup measure only considers the I component. When anti-windup halt and I component are enabled, the anti-windup halt measure corrects the I component such that: AWMIN ≤ yi ≤ AWMAX.
Limited Rise of wh and yh
The parameters vwh and vyh represent velocity limiters for the manual values wh and yh. A 0 value disables the functionality of the corresponding velocity limiter (vwh = 0 or vyh = 0, respectively). The wh and yh values are then utilized without delay.