Addressing
(Original Document)
About us
Flat Addressing
This module requires 7 contiguous, 16-bit input words (%IW), and 5 contiguous, 16-bit output words (%QW).
Topological Addressing
Topological addresses for the 140ERT85410 Time Stamp Module:
Point
I/O Object
Comment
Input 1
%IW[\b.e\]r.m.1.1
Data
• • •
Input 7
%IW[\b.e\]r.m.1.7
Data
Output 1
%QW[\b.e\]r.m.1.1
Data
• • •
Output 5
%QW[\b.e\]r.m.1.5
Data
Used abbreviations: b = bus, e = equipment (drop), r = rack, m = module slot.
Note
The above described addressing is for information only. Direct access to the modules raw data is not recomended. All data exchange should be performed through the EFBs for the ERT module.