This bit is set to 1 during the first complete restored cycle of the PLC either in RUN or in STOP mode. It is reset to 0 by the system before the following cycle.

To detect the first cycle in run after cold start, refer to %SW10.

It is reset to 0 by the system at the end of the first complete cycle and before the outputs are updated.

An internal timer regulates the change in status of this bit.

It is asynchronous in relation to the PLC cycle.

Normally at 1, this bit is set to 0 when an error on the embedded I/O or device on a network is detected (e.g. non-compliant configuration, exchange fault, hardware fault, etc.). The %S10 bit is reset to 1 by the system when all the detected errors have disappeared.

Normally at 0, this is set to 1 by the system as soon as the task execution time becomes greater than the maximum execution time (i.e., the watchdog) declared in the task properties.

This bit is set to 1 by the system when the PLC is in RUN.

It is set to 0 by the system as soon as the PLC is no longer in RUN (STOP, INIT, etc.).

First cycle after switching to RUN.

Switching the PLC from STOP mode to RUN mode (including after a cold start with automatic start in run) is indicated by setting system bit %S13 to 1. This bit is reset to 0 at the end of the first cycle of the MAST task in RUN mode

Normally set to 0, this bit is set to 1 when the destination zone for a character string transfer is not of sufficient size (including the number of characters and the end of string character) to receive this character string.

The application stops in error state if the %S78 bit is to set to 1.

This bit must be reset to 0 by the application.

Normally set to 1, this bit is set to 0 by the system when a fault on an in-rack module is detected (For example, non-compliant configuration, exchange fault, hardware fault, etc.).

This bit must be set to 1 by the user.

Rotate shift output

Normally at 0.

During a rotate shift operation, this bit takes the state of the outgoing bit.

Normally set to 0, this bit is set to 1 by the system in the event of a time period overrun (i.e., task execution time is greater than the period defined by the user in the configuration or programmed into the %SW word associated with the task). The user must reset this bit to 0. Each task manages its own %S19 bit.

Normally set to 0, this bit is set to 1 when the address of the indexed object becomes less than 0 or exceeds the number of objects declared in the configuration.

In this case, it is as if the index were equal to 0.

Test the user program after each operation where overflow may occur, then reset to 0 if there is indeed an overflow.

When the %S20 bit switches to 1, the application stops in error state if the %S78 bit has been to set to 1.

The bit %S21 indicates the first cycle of MAST task, including after a cold start with automatic start in run and a warm start.

%S21 is set to 1 at the start of the cycle and reset to zero at the end of the cycle.

Normally set to 1. The master task is deactivated when the user sets the bit to 0. This bit is taken into consideration by the system at the end of each MAST task cycle.

The %S40 bit is assigned to rack 0.

The switch from 1 to 0 updates the real-time clock with the values entered in words %SW50…%SW53.

The system-managed bit set to 1 indicates that the real-time clock is missing or that its system words (%SW50…%SW53) are meaningless. In this case, the clock must be reset to the correct time.

This bit is set to 1 by the user to start a backup operation. The system will detect the rising edge to start the backup. The state of this bit is polled by the system every second. A backup takes place only if the application in RAM is different from the one in the flash.

This bit is set to 0 by the system when the backup is finished.

Warning:Before creating a new backup by setting bit %S66 to 1, you must test that bit %S66 has been set to 0 by the system (which means the previous backup is finished). Never use %S66 if it is set to 1. This may lead to a loss of data.

Bit %S66 is particularly useful after replacement of initial value %S94 and save parameters.

Normally at 0, this bit can be set to 1 by the user, to program a PLC stop on application fault: %S15, %S18, %20.

Normally set to 0, this bit can be set to 1 to reset the message counters %SW80 to %SW86.

Normally at 0, this bit can be set to 1 by the user to replace the initial values of the declared variables with a ‘Save’ attribute (For example, DFB variables) with the current values.

The system resets the bit %S94 to 0 when the replacement is made.

This bit compares the application as executed in RAM versus the internal backup saved to flash. Values are:

0: application backup not consistent. This state is obtained when application is auto modified (saveparam or replace init value) and not saved using %S66.

1: application backup is consistent

0: both Ethernet port link down

1: at least one port link up

Normally at 1, this bit is at 0 on detection of a fault in a device on CANopen

This word is used to modify the period of the master task via the user program or via the terminal.

The period is expressed in ms (1...255 ms) %SW0=0 in cyclic operation.

On a cold restart: it takes the value defined by the configuration.

If the value of the current task bit is set to 0, it means that the task is performing its first cycle after a cold start.

Reads the duration of the watchdog. The duration is expressed in milliseconds (10...1500 ms).

This word cannot be modified.

Gives the Modbus slave address of the CPU serial port. Modification is not taken into account. it is 0 if the CPU does not have a Serial Port link.

This word contains the current Operating System (OS) version of the PLC processor.

Example: 16#0135

version: 01

issue number: 35

This word contains the commercial version of the PLC processor patch.

It is coded onto the least significant byte of the word.

Coding: 0 = no patch, 1 = A, 2 = B...

Example: 16#0003 corresponds to patch C.

This word contains the Firmware version number in hexadecimal of the PLC processor firmware.

Example: 16#0011

version: 2.1

VN: 17

This word is reset to 0 by the system on cold start, and also by the program for re-usage purposes.

%SW18 represents the least significant bytes and %SW19 the most significant bytes of the double word %SD18, which is incremented by the system every 1/10th of a second. The application can read or write these words in order to perform duration calculations.

%SD18 is incremented systematically, even in STOP mode and equivalent states. However, times when the PLC is switched off are not taken into account, since the function is not linked to the real-time scheduler, but only to the real-time clock.

For Quantum safety PLC, knowing that the 2 processors must process exactly the same data, the value of %SD18 is updated at the beginning of the mast task, and then frozen during the application execution.

This system word allows to verify on server side the number of requests processed by PLC per second.

The system overhead time depends on the configuration (number of I/O) and on the current cycle requests (communication, diagnostics).

System overhead time = Mast Cycle Time - User code execution time.

This can be read and written by the user program or by the terminal.

This word indicates the execution time of the last master task cycle (in ms).

This word indicates the longest master task execution time since the last cold start (in ms).

This word indicates the shortest master task execution time since the last cold start (in ms).

These words are managed by the system when the bit %S50 is set to 0.

These words can be written by the user program or by the terminal when the bit %S50 is set to 1.

For M580:

The current time is in UTC (Coordinated Universal Time). If a local time is needed, use the RRTC_DT function.

Contains two 8-bit series to adjust the current date.

The action is always performed on the rising edge of the bit.

This word is enabled by bit %S59=1.

System word containing the number of the week in the year: 1…52 (in BCD).

Result of the last registration

= 0 if the recording was successful

= 1 if the diagnostics buffer has not been configured

= 2 if the diagnostics buffer is full

Result of the last de-registration

= 0 if the non-recording was successful

= 1 if the diagnostics buffer has not been configured

= 21 if the error identifier is invalid

= 22 if the error has not been recorded

Number of errors currently in the diagnostics buffer.

These words are updated by the system, and can also be reset using %S80.

These words are updated by the system, and can also be reset using %S80.

This word is updated by the system, and can also be reset using %S80.

Number of requests processed by synchronous server per master (MAST) task cycle.

The requests processed may come from all communication ports.

N=4(minimum 2, maximum 4 + 4 = 8)

The code of the last fault detected is given in this word. The following error codes cause the PLC to stop if %S78 is set to 1.

Address of the instruction that generated the application blocking error.

0 = not initialized 1 = IP initialized 3= link ETH down 4= IP duplicate 5 = Wait for server 6= no conf or conf error 7= configuration conflict

bit 0: reserved

bit 1: 0 in case of error on HSC, else 1

bit 2: 0 in case of error on DDM, else 1

bit 3: 0 in case of error on AMI, else 1