Remote I/O and Distributed I/O Defined Architecture: Junctions
Original instructions
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Introduction
A Quantum EIO network can accept the addition of distributed I/O traffic through a DRS. The DRS can accept distributed I/O data form either of following 2 sources:
Each junction presents the queueing point, which can add delay — or jitter — to the system. If 2 packets simultaneously arrive at a junction, only 1 can be immediately transmitted. The other waits for a period referred to as “1 delay time” until it can be transmitted.
Because remote I/O packets are granted priority by the Quantum EIO network, the longest a remote I/O packet can wait at a junction is 1 delay time before it is transmitted by the device or switch.
The following scenarios depict how different junction types handle distributed I/O packets that arrive simultaneously with remote I/O packets.
Switch
In the following example, a switch receives a steady flow of packets from both the main remote I/O ring and a distributed I/O sub-ring:
The switch handles remote I/O packets in the following sequence:
Time
Remote I/O Ring In
Distributed I/O Sub-ring
Remote I/O Ring Out
Comment
T0
1
a (started)
–
packet “1” arrived after transmission of packet “a” begins
T1
2
b
a
packets “2” and “b” arrive simultaneously
T2
3
c
1
packets “3” and “c” arrive simultaneously
T3
4
d
2
packets “4” and “d” arrive simultaneously
T4
5
e
3
packets “5” and “e” arrive simultaneously
Switch with Sub-ring Cable Break
In the following example, a switch receives a steady flow of packets from the remote I/O main ring and also from both segments of a distributed I/O sub-ring with a cable break:
The switch handles remote I/O packets in the following sequence:
Time
Remote I/O Ring In
Distributed I/O Sub-ring A
Distributed I/O Sub-ring B
Remote I/O Ring Out
Comment
T0
1 (started)
a
p
–
packets “a” and “p” arrive after transmission of packet “1” begins
T1
2
b
q
1
packets “2” , “b” and “q” arrive simultaneously
T2
3
c
r
2
packets “3”, “c” and “r” arrive simultaneously
T3
4
d
s
3
packets “4”, “d” and “s” arrive simultaneously
T4
5
e
t
4
packets “5”, “e” and “t” arrive simultaneously