Contents
|
Function
|
---|---|
Digital inputs 1 ... 16
|
Digitally processed input data which is cyclically updated (the module’s input address corresponds to that of the digital standard input modules, i.e. inputs 1 16 correspond to bits 15 0)
|
Digital inputs 17 ... 32
|
|
Transfer status
|
IN transfer status (TS_IN)
|
MUX 1
|
Multiplex data block for block transfer, such as:
|
MUX 2
|
|
MUX 3
|
|
MUX 4
|
Contents
|
Function
|
---|---|
Transfer status
|
OUT transfer status (TS_OUT)
|
MUX 1
|
Time data block for the ERT for the clock synchronization
|
MUX 2
|
|
MUX 3
|
|
MUX 4
|