Time Synchronization
Original instructions
About us
Overview
The BMXERT1604T/H module receives the broadcast time code input from the IRIG port, DCF port, or via X-bus (only 1 format is allowed at a time).
The external time codes not only provide the year, month, day, hour, minute, and second (IRIG-B) information, but also provide the on time edge at each second (IRIG-B) or minute (DCF77). This enables to synchronize the internal clock of the module with the external clock.
The following parameters are provided to support the time synchronization function:
Parameter Type
Parameter Name
Valid Values
Details
Configuration
Clock SYNC source
0: Free running/internal clock
1: DCF77/external clock
2: IRIG-B/external clock (default)
3: CPU/CRA head/external clock
Effective range:
Module
Organization:
Group 0
Implicit
TIME_VALID
0: Invalid
1: Valid
Available in:
Device DDT
IODDT
Debug screen
Implicit
CLOCK_FAILURE
0: No fail
1: Fail
Available in:
Device DDT
IODDT
Debug screen
Implicit
CLOCK_NOT_SYNC
0: Synchronized
1: Not synchronized
Available in:
Device DDT
IODDT
Debug screen
Clock SYNC Source
Source
Type
Description
Free running
Internal clock
The module uses the internal clock. After the module is initialized, the start time is changed to 1970-01-01 00:00:00:000 as defined in IEC61850.
DCF77
External clock
Timing is synchronized to a timing code received on the DCF input port.
IRIG-B
External clock
Timing is synchronized to a timing code received on the IRIG input port.
CPU/CRA head
External clock
Timing is synchronized via X-Bus, with:
  • the CPU when the BMXERT1604T/H module is located on the local drop.
  • the CRA head when the BMXERT1604T/H module is located on a remote X80 drop.
NOTE: When the external clock options are selected, the BMXERT1604T/H module stays in the free running mode (begins from 1970-01-01 00:00:00:000 after initialization) till the first successful synchronization with the external clock.
Clock Failure
An error message bit activates if the module detects that the time frame is invalid. When the external clock source is selected, an error message bit is asserted and the external time clock is detected as invalid.
The following conditions are considered invalid time frames, when:
This bit is cleared when a valid time frame is received and is continuous to current internal time. The initial value will be 1 after start.
NOTE: When the free running/internal clock option is selected, CLOCK_FAILURE always keeps 0.
Clock Not SYNC
When the external clock source is selected, the synchronizing effort reaches 10 s (IRIG-B) or 10 min. (DCF-77, or CPU/CRA head) without success, this bit is asserted to declare the CLOCK_NOT_SYNC. And it will be cleared once the time is synchronized. After initialization, this bit keeps 1 till the first successful synchronization.
NOTE: When the free running/internal clock option is selected, CLOCK_NOT_SYNC always keeps 1.
Time Valid
The value of this bit is decided by Clock SYNC source option, and the state of CLOCK_FAILURE and CLOCK_NOT_SYNC bits.
The (T) LED on the display panel which denotes the synchronization status acts base on the combination of these parameters:
Clock SYNC Source
CLOCK_FAILURE
CLOCK_NOT_SYNC
TIME_VALID
LED (T) (green)
IRIG-B, DCF77, or CPU/CRA head
0
0
1
ON
IRIG-B or DCF77
1
0
0
FLK
CPU/CRA head
0
1
0
IRIG-B, DCF77, or CPU/CRA head
1
1
0
OFF
Internal Clock
0
1
0
NOTE: Any status of the time quality bits (TIME_VALID, CLOCK_FAILURE, CLOCK_NOT_SYNC) will not stop the event recording for BMXERT1604T/H module.
NOTE: With an IRIG-B external clock, if IEEE1344 or IEEE C37.118 standards are not supported, then CLOCK_FAILURE and CLOCK_NOT_SYNC bits can be set to 1 during the switch between daylight saving time and standard time.
In any case, 13 seconds (IRIG-B external clock) or 13 minutes (DCF77, or CPU/CRA head external clock) after switch between daylight saving time and standard time, stamping time is synchronized with the external clock regardless the error bits status. Once synchronized, CLOCK_FAILURE and CLOCK_NOT_SYNC bits are reset.
Catch-up Mode
When the "on-time" edge is acquired from an external source, the BMXERT1604T/H module compares the newly acquired time with the (current) internal running time:
Comparison
Action
The new time is later than the internal running time.
The internal time is immediately updated to reflect the external time.
The new time is earlier than the internal running time.
The BMXERT1604T/H implements the catch-up mode, as described below.
In catch-up mode, the module retains the externally synchronized time, and the time stamp for thenext incoming event is the result of the equation last event stamp + 0.5 ms:
If the current externally synchronized time is later than the time stamp of the last event, the synchronized time can be used directly for the new incoming event, and catch-up mode is terminated.
NOTE: During the catch-up mode, TimeAccuracy value is set to 0xx11011 for the recorded events to indicate the ClockInSync status.