Phase
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Description
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1
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A Module or Bus error is registered by the DFB in case of a break in the AS-Interface supply, bit 0 in STATUS and bit 2 in STGENE are set to 1.
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2
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A slave with 0 address is detected on the AS-Interface bus, bit 1 in STGENE is set to 1.
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3
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AS-Interface power is restored, but the Module or Bus error is not erased because a slave with 0 address is still detected on the AS-Interface bus.
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4
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The slave with 0 address is no longer detected on the AS-Interface bus, the error has disappeared. The STATUS and STGENE words are set to 0.
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5
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An Absent Slave(s), Not configured slave(s) or Error Slave(s) error is built into the STATUS word (bit = 1, 2 or 3) and bit 10 of STSLABS[0], STSLNC[0] or STSLKO[0] or STSLKO[0] is set to 1 indicating that AS-Interface slave 10 is in error.
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6
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AS-Interface slave 14 is disconnected, only bit 14 of STSLABS[0], STSLNC[0] or STSLKO[0] is set to 1.
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7
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AS-Interface slaves 10 and 14 are again present on the AS-Interface Bus. Bit 1 of STATUS is set to 0 and STSLABS[0], STSLNC[0] or STSLKO[0] are set to 0.
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