The ratio mode only uses the IN_A and IN_B inputs. This counting mode consists of two sub-modes:
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Ratio 1: is used to divide two frequencies (Frequency IN_A / Frequency IN_B) and is useful, for example, in applications such as flowmeters and mixers.
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Ratio 2: is used to subtract two frequencies (Frequency IN_A - Frequency IN_B) and is used in the same applications but which require more precise adjustment (closer frequencies).
NOTE: A positive value indicates that the frequency measured on the IN_A input is greater than the frequency measured on the IN_B input.
A negative value indicates that the frequency measured on the IN_A input is less than the frequency measured on the IN_B input.
The figure below shows BMX EHC 0200 module operation in Ratio 1 mode.
In this mode, the counter evaluates the ratio between the number of rising edges of the IN_A input and the number of rising edges of the IN_B input over a period of 1 s. The register value is updated every 10 ms.
An absolute limit value is declared on the configuration screen. If this limit value is exceeded, the counter_value register (%IDr.m.c.12) is disabled by setting the validity bit (%IWr.m.c.0.3) to 0.
If no frequency is applied to the IN_A or IN_B inputs, the counter_value register (%IDr.m.c.12) is disabled by setting the validity bit (%IWr.m.c.0.3) to 0.
NOTE: The ratio 1 mode presents the results in thousandths in order to have greater level of precision (where 2,000 is displayed, this corresponds to a value of 2).
The figure below shows BMX EHC 0200 module operation in Ratio 2 mode.
In this mode, the counter evaluates the difference between the number of rising edges of the IN_A input and the number of rising edges of the IN_B input over a period of 1 s. The counter_value register (%IDr.m.c.12) is updated at the end of each 10 ms interval.
An absolute limit value is declared on the configuration screen. If this limit value is exceeded, the counter_value register (%IDr.m.c.12) is disabled and the validity bit (%IWr.m.c.0.3) to 0.
Counter Status Bits in Ratio Mode
The table below shows bits that are used by the status word %IWr.m.c.0 when the counter is configured in ratio mode:
|
Bit
|
Label
|
Description
|
|
%IWr.m.c.0.3
|
VALIDITY
|
Validity bit is used to indicate that the counter current value (ratio value) and compare status registers contain valid data.
If the bit is set to 1, the data is valid.
If the bit is set to 0, the data is not valid.
|
|
%IWr.m.c.0.4
|
HIGH_LIMIT
|
The bit signals a error when the ratio exceeds the absolute limit.
The bit is set to 1 when frequency to IN_A becomes too fast.
The bit is reset to 0 when the frequency to IN_A remains correct.
|
|
%IWr.m.c.0.5
|
LOW_LIMIT
|
The bit signals a error when the ratio exceeds the absolute limit.
The bit is set to 1 when frequency to IN_B becomes too fast.
The bit is reset to 0 when the frequency to IN_B remains correct.
|
In this mode, the type of the IODDT must be T_SIGNED_CPT_BMX.
The maximum frequency that the module can measure on the IN_A and IN_B inputs is 60 kHz.
The measured values are between -60,000,000,000 and +60,000,000,000.
NOTE: You have to check the validity bit (%IWr.m.c.0.3) before taking into account the numerical values such as the counter and the capture registers. Only the validity bit at the high level (set to 1) guarantees that the mode will operate correctly within the limits.
