BMX EHC 0200 Module Operation in Event Counting Mode
Original instructions
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At a Glance
Using the event counting mode allows you to determine the number of events received in a scattered manner.
Basic Principle
In this mode, the counter assesses the number of pulses applied at the IN_A input, at time intervals defined by the user. The counting register is updated at the end of each interval with the number of events received.
It is possible to use the IN_SYNC input over a time interval, provided that the validation bit is set to 1. This restarts the event counting for a new predefined time interval. Depending on the selection made by the user, the time interval starts at the rising edge or at the falling edge on the IN_SYNC input.
Operation
The trend diagram below illustrates the counting process in event counting mode:
Counter Status Bits in Event Counting Mode
The table below shows the composition of the counter’s %IWr.m.c.0 status word in event counting mode:
Bit
Label
Description
%IWr.m.c.0.2
SYNC_REF_FLAG
The bit is set to 1 when the internal time base has been synchronized.
The bit is set to 0 when the sync_reset command is received (rising edge of the %Qr.m.c.8 bit).
%IWr.m.c.0.3
VALIDITY
Validity bit is used to indicate that the counter current value (events number) and compare status registers contain valid data.
If the bit is set to 1, the data is valid.
If the bit is set to 0, the data is not valid.
%IWr.m.c.0.4
HIGH_LIMIT
The bit is set to 1 when the number of received events exceeds the counter size.
The bit is reset to 0 at the next period if the limit is not reached.
%IWr.m.c.0.5
LOW_LIMIT
The bit is set to 1 when more than one synchronization is received within 5 ms period.
The bit is reset to 0 at the next period if the limit is not reached.
Type of the IODDT
In this mode, the type of the IODDT must be T_UNSIGNED_CPT_BMX.
Operating Limits
The module counts the pulses applied at the IN_A input every time the pulse duration is greater than 5 μs (without debounce filter).
The synchronization of the counter must not be done more than one time per 5 ms.
NOTE: You have to check the validity bit (%IWr.m.c.0.3) before taking into account the numerical values such as the counter and the capture registers. Only the validity bit at the high level (set to 1) guarantees that the mode will operate correctly within the limits.