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Communication fault on starting Profibus DP:
This fault can be caused by poor configuration or damage to the cable. In this case, the bus remains in a non-operational state and the slaves remain in failed start state.
An error code is generated by the TSX PBY 100 master module in the form of diagnostics. All the diagnostics bits of the slaves remain in their fault state. The ERR LED is on and the other LEDs are off.
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Communication fault during operation:
If a fault occurs while exchanges are in progress, an error code is generated by the TSX PBY 100 master module in the form of diagnostics. In this case, the slaves switch to their pre-configured default state after the watchdog period is exceeded.
The diagnostic bits of the slaves are enabled to indicate that the slaves are not available and that inputs are reset to zero. The TSX PBY 100 module saves the diagnostics and informs the CPU of their availability using the language object %IWr.m.0.243.10...12.
TSX PBY 100 master module faults
When a fault appears, data exchanges, commands and diagnostics are interrupted. After the watchdog period is exceeded, an error code is generated in the form of diagnostics.
If exchanges are interrupted, the diagnostics bits of the slaves are enabled to indicate that the slaves are not available and that inputs are reset to zero. The ERR LED is on and the other LEDs are off.
When exchanges are in progress, a slave fault is indicated by a new diagnostic. If communication is still established, the slave generates the diagnostics, if not, the diagnostics are generated by the TSX PBY 100 master module.
The diagnostics bits of the slave are enabled to indicate that the slave is not available and that its inputs are reset to zero. The TSX PBY 100 module saves the diagnostics and informs the CPU of their availability using the language object %IWr.m.0.243.10...12.
NOTE: If one or several slaves are faulty, the bus cycle slows down. Several PLC cycles may be necessary for diagnostics to be recognized and inputs to be reset to zero.
In the event of a communication fault between the CPU and the TSX PBY 100 module, all outputs are set to their default state (maintained or Reset) and inputs are reset to zero. The ERR LED flashes to indicate the communication fault between the PLC CPU and the TSX PBY 100 module.
The transfer of diagnostics data between the master and the slave are not affected.
Resetting outputs after loading a project
For a low baud rate (less than 500 Kbit/s) and a large watchdog value, the slaves maintain their output states for the whole of the watchdog period.
For a low baud rate (less than 500 Kbit/s) and a disabled watchdog, the slave output states are maintained until the project loading has finished.
