Templates, Codes & Sctipt for Book
a simple VHDL template file temp.vhd (for chapter 1 of VHDL book)
a simple DO template file temp.do under Modelsim (for chapter 1 of VHDL book)
a more complex DO template file temp.do under Modelsim (for chapter 1 of VHDL book)
a simple VHDL template file tb_temp.vhd for Test bench (for chapter 7 of VHDL book)
a simple DO template file rv_temp.do under Riviera-Pro
TCL script template for assigning DE2 board
TCL script template for assigning DE2-115 board
TCL script template for assigning DE1 board
TCL script template for assigning DE0 board
TCL script template for assigning DE-nano board
TCL script template for assigning DE0-Nano board
TCL script template for assigning ASK2CB board
TCL script template for assigning A-C4E6 board
TCL script template for assigning ZR_tech board
TCL script template for assigning DE0-CV board
TCL script template for assigning DE10-Lite board
TCL script template for assigning QQ-FPGA board (CYCLONE II device & pins) - qq_pins.tcl
Xilinx XDC script template for assigning BASYS3 board (with Artix-7 device) - basys3_pins.XDC
TCL script template for assigning UP3 borad (CYCLONE I device & pins) - up3_pins.tcl
TCL script template for assigning APEX-NIOS board (APEX device & pins) - nios_pins.tcl
TCL script template for assigning UP2 borad (FLEX-10K70 device & pins) - up2_pins.tcl
TCL script template for assigning UP1 borad (FLEX-10K20 device & pins) - up1_pins.tcl
TCL script template for assigning UP1/UP2 board (MAX-7K device & pins) - up1_max.tcl
A script for making Modelsim support Altea LPMs & Atoms - make_altera.do
A script for making Riviera-Pro support Altea LPMs & Atoms (Compiling source files) - make_altera_rv.do
A script for making Riviera-Pro support Altea LPMs & Atoms (using Pre-Compiled files) - make_altera_rv_pre_vhdl.do
Help you run a Gete-Level simulation (with Modelsim) from a Quartus mixed project
Help you run a Source-Level simulation (with Modelsim) from a Quartus mixed project
A cleaner batch file (old) - clean.bat
Making Wave window of (old) Modelsim have non dark colors - nice_colors.tcl
Making Wave window of (old) Modelsim have Black & White colors - bw_colors.tcl
הדגמת הורדת קובץ סקריפט מאתר זה עבור לוח התרגול
Altera הדגמת בחירת הרכיב והקצאת הדקים באמצעות הסקריפט, שמירת הסקריפט והרצתו - כפי שמוסבר בספר
a simple MIF template file (temp.mif) for my VHDL & Altera books
a simple Verilog template file (temp.v)
a simple Verilog header file (my_header.v)
a simple Verilog test bench template file (tb_temp.v)
a simple AHDL template file (temp.tdf)
a simple ABEL template file (temp.abl)
Hardware Debug - Example from chaptera 7 of Altera Book (QAR - Quartus Archived File)
בחינות ממשלתיות של מה"ט (C+VHDL)
חזרה לדף הראשי
