The time stamped event logging requires a precise internal clock. The ERT module uses a software clock for creating the time in millisecond intervals. This software clock is normally synchronized with the help of an external time signal (standard time receiver) in one minute intervals. It can also be synchronized via a telegram or be free running.

The incoming time signal is checked for plausibility. Runtime deviations from the software clock are corrected. The time reception takes a few minutes before the time becomes available after startup. The software clock is synchronized to this time. The module then determines the deviation from the software clock with regard to the external clock within a specific period, and offsets the deviation accordingly. This is carried out continuously during the entire runtime. After a few hours runtime (generally within 2 hours) the software clock reaches maximum precision.

If implausible or incorrect time messages are received, the software clock continues running without synchronization. The deviation gets larger during this time. If this time phase does not exceed the "Validity Reserve" specified, the clock resynchronizes when the next valid time information is received. However, if the time period is exceeded before the module receives a valid time signal, the ERT sets bit "Time Invalid" in the "Status" output word (bit 3 - TU), returned by the "ERT_854_10" transfer EFB (see ERT_854_10: Data transfer EFB). All time stamps set after this are invalid (the high priority byte for millisecond information is set to FF). The bit is reset as soon as the next valid time message is received.

If the module receives no valid time messages for 10 minutes, the ERT sets the bit "Time Reference Error" in the "Status" output word (bit 2 - TE), returned by the "ERT_854_10" transfer EFB (see ERT_854_10: Data transfer EFB). The bit is reset as soon as the next valid time message is received.

The synchronization is possible by the PLC using "ERT_854_10" EFB (low precision).

The DCF 77E receiver delivers a 24VDC signal in DCF77 format and can supply up to 16 ERT modules concurrently. The BCD coded time signal is transferred once a minute and synchronizes the ERT minutes changeover. When the ERT is restarted the software clock is synchronized within three minutes of receiving the first information. After this the ERT software clock time matches the standard time sender. If the send signal becomes unavailable the free running software clock can still be used but is not as precise. The DCF sender delivers CET (Central European Time), takes into account summer/winter time changes as well as seconds and years transitions.

A GPS receiver must be used for applications which use GPS satellite time references. The module demodulates the GPS signal and delivers DCF77 format output signal from 24 VDC. The ERT decodes the signal and synchronizes the minutes transition for the internal software clock. GPS satellites sends UTC time (Universal Time Coordinated) which GMT (Greenwich Mean Time = Western European Time) corresponds to. Seconds and years transitions are taken into account. The recommended validity reserve for the DCF/GPS time base signal is one hour (the settings range for DCF/GPS sync is between 1 and 5 hours). Several ERT modules can be synchronized simultaneously using a GPS receiver.

If a clock only requires a lower precision, the ERT internal software clock can be synchronized with a time value sent by the master. The software clock runs freely until the next time value is received. Precision is usually within 100 milliseconds per hour and the software clock must be synchronized correspondingly often. The "ERT_854_10" transfer EFB provides the required time synchronization. This means several ERT modules can be supplied with almost the same time; the time source used is the derived data structure "DPM_Time". The validity reserve setting for the EFB synchronized internal software clock moves between 1 and 254 hours). However, if the time period is exceeded before the next transfer of a time signal, the ERT sets bit "Time Invalid" in the "Status" output word (bit 3 - TU), returned by the "ERT_854_10" transfer EFB. All time stamps set after this are invalid (the high priority byte for millisecond information is set to FF). The bit is reset as soon as the next valid time message is received.

The ERT internal software clock can also be used on its own. Setting the validity reserve for the internal software clock to 0 activates duration mode, shown by the bit "Time not synchronized" in the "Status" output word (bit 4 - TA) which is returned by the "ERT_854_10" transfer EFB. In this case there is no validity reserve that can be exceeded and therefore no invalid time stamps. The bits "External Reference Error" and "Time Invalid" in the output word "Status" (Bit 2/3 - TE/TU) are never set; the time starts automatically without synchronization. The default start settings for the internal clock is 0 hours, 1/1/1990. The time settings can be made using: