IEC 60870-5-101/104 Master/Client

Predefined Master Commands

The predefined master command of the IEC 60870-5-101/104 master contains these fields:

Command	Status	Meaning
C_SC	Yes	Single point command
C_DC		Double point command
C_RC		Regulating step command
C_SE_A		Set point command, normalized value
C_SE_B		Set point command, scaled value
C_SE_C		Set point command, short floating value
C_BO		32 bits, bit string command
C_IC		Interrogation command
C_CI		Counter interrogation command
C_RD		Read command
C_CS		Clock synchronization command
C_TS		Test command
C_RP		Reset process command

NOTE: When the C_DC address does not receive RTU master command, its initialization value is 0 and is an invalid value in the C_DC_NA_1 control command by default. When the master controls this address, the value is 1 or 2 to switch on or off.

Command Implementation Method

Commands can be mapped to the CPU memory in one of the following manners:

32-bit CPU register (command and status) through %MW. Both the command and status are 16 bits.
64-bit CPU register (command and status) through %MW. Both the command and status are 32 bits.

Commands are implemented each time when the value in the configured CPU memory changes. The user can easily control the command implementation by changing the value in the CPU memory.

NOTE: In order to support re-send pulse in IEC101 master and IEC104 client, the C_SC_NA and C_DC_NA are triggered to send out on the change of low byte of CPU mapping (%MW) since firmware V1.6 (instead of a change of last bit of CPU mapping (%MW) in earlier firmware versions).

Command Status Register

Certain commands have a status register that let the user know if the command was successfully executed. The status register is a 16-bit word or 32-bit word. For example, if a command is mapped to CPU register %MW1, the corresponding status register is automatically mapped to %MW2.

NOTE: When a command is mapped to a register and the command has a command status, the status register is automatically mapped to the following register.

If a command has a result, the low byte of the status register increment by 1 to indicate that the status is for the command. The high byte is the status of the command.

NOTE: If the high byte of command status has a result 0, this means that it has completed successfully.

An IEC command status register contains these fields:

Status Value	Description
0	The command has completed successfully.
1	A response was received but the requested command is not yet complete.
2	The command did not transmit as expected.
3	The command has timed out.
4	The command has been canceled.

P/N Control for Control Points (Firmware V1.7 or Later)

P/N bit in the Cause of Transmission field can be either controlled automatically or manually.

The P/N bit can be controlled manually for the following control point types:

C_SC
C_DC
C_RC
C_SE_A
C_SE_B
C_SE_C
C_BO

To control the P/N bit:

Configure the CMD_QUALITY parameter:
- Ctrl Point Type: Select the control point type.
- IOA: Start IOA that corresponds to the control point type selected.
- Point Count: Control point range from IOA.
- CPU Register Address: %MW dedicated to manage the P/N bit.
- Variable Name: Variable associated with %MW.

Behavior when the quality of control point is configured (manual control):

The master sends a command.
The IEC stack checks for CMD_QUALITY settings (%MW associated to quality bit).
- If the CPU program accepted the command, it puts to 0 the equivalent of P/N bit 7 in %MW. The master receives a valid quality reply.
- If the CPU program did not accept the command, it puts to 1 the equivalent of P/N bit 7 in %MW. The master receives an invalid quality reply.

Behavior when quality of control point is not configured (automatic control):

The master sends a command.
The IEC stack manages P/N bit automatically.