The 140 EHC 202 00 high speed counter requires six contiguous output (4X) and six contiguous input (3X) registers in the I/O map.

The 4X registers perform the same configuration tasks as in the Parameter Configuration. Also, the preset and the enable inputs connected to the field wiring terminal block perform the same functions as those software command control bits. When both methods are used to:

For simple applications, the parameter configuation rather than the I/O mapped registers can be used to configure the module. Parameter configuration is only possible while the PLC is stopped. The selected parameters take effect when the PLC is set to run. For applications that require that module parameters be changed while the system is running, user logic can modify the I/O map-assigned registers to override the previously selected parameters.

When using either parameter configuration or I/O map registers, the maximum values specified in the Load Values Command section are the largest values that can be used by the module.

The I/O Mapped registers discussed in this section are 4X output registers that:

3X input registers that:

There are four command that can be performed. Each uses one or more of both types of registers assigned to the module. In addition to the command definition byte, the first 4X register for all commands contain control bits to preset and enable/disable counters of either channel.

Command 1 uses three 4X registers and six 3X registers (see below).

This command does the following:

There are four formats for this command. It uses up to six 4X registers and six 3X registers.

Values loaded may be the following.

Command 3 uses one 4X register and six 3X registers (see below).

Command 4 uses one 4X register and six 3X registers (see below).

The following details the command words and responses.

The LOAD VALUES 4X register format depends on the Counter/Rate Sample mode selected in Command 1, Register 4X+1, bits 11 and 12.

If configured for two, 16 bit Counters - Output Assert ON, the following information is displayed.

If configured for one, 32 bit Counter - Output Assert ON, the following information is displayed.

If configured for 2, 32 bit Counters - NO Output Assert, the following information is displayed.

If configured for Rate Sample Mode, the following information is displayed.

The most significant bit in the I/O Map status byte is used for the 140 EHC 202 00 High Speed Counter Module.

Field connections for this example are illustrated in the EHC 202 wiring diagrams 1-4. The maximum allowable Vref value is 30 VDC. Input pulse on-off threshold levels for the 5 ... 24 VDC Vref range are listed in the module specification table. The minimum differential input is 1.8 V.

The following user logic:

In this example, block moves are used to load the operating parameters into the module. This requires pre-defined tables be established. Register values are in HEX format.

Zeros in the 4X registers also mean no change. Setpoint, maximum count and assert time can only be set to zero using the parameter configuration. When the registers in this example are echoed, zeros will appear but the actual content in the module will be unchanged from previous values. In this example, Counter 2 is disabled and its outputs and timed assert have not been selected. Registers 400204 - 6 have no meaning.

After the module executes the Configure and Load Value’s commands, they are echoed in the I/O mapped 3X registers except for the command register’s low 8 bits. Command execution time by the module is 1 ms. Actual time between the 4X register block move and the echo response display in the 3X registers is dependent on User Logic and hardware configuration. An echo of the Configuration command registers would appear as follows:

When this command is issued, the content of the input pulse counter is retrieved. The 3X register content would appear as follows:

If register 400103 in the Module Configuration Table has been set to 4200, Output 1A would have been latched on at setpoint and Output 1B latched on at maximum count. Wiring Diagrams 2 and 4 show how the encoder Z outputs could be used to reset the latched outputs. The minimum pulse width to reset outputs is 1 ms.

The COUNT DOWN example uses the same wiring as in the count up example, except the Input 1B+ level is changed to common (connected to Vref-) for Pulse Inputs illustrated in Wiring Diagrams 1 and 2. For Quadrature Inputs, no wiring change is required as the count direction is decoded internally by sensing the phase shift change between inputs A and B.

The User Logic is the same as for the count example. The actual operation of the module is different in that the output associated with maximum count turns on after zero count has been reached.

The example configures the module to decrement the input count from the maximum value, turn on an output at a setpoint value of 50, and turn on a second output after the input counter had reached zero and rolled over to the maximum count; the operation is then repeated. The initial loading of the maximum count will not cause its associated output to turn on.

Field connections for this example are illustrated in the Wiring Diagrams1-4. The connections on terminals 15 and 16 are optional, depending on the use requirements of the outputs. Terminals 39 and 40 always require the 24 VDC supply connections. The maximum allowable Vref value is 30 VDC. Input pulse on-off threshold levels for the 5 ... 24 VDC Vref range are listed in the module specification table. The minimum differential input is 1.8 V.

As with count examples, tables are set up and transferred to the module using block moves. The User Logic for Rate Sample is the same as that used for Pulse Input Count Up/Down.

When this command is issued, the input pulse counter content is retrieved. The 3X register content is the count over the time period selected in the Load Values registers 4X + 1 and 4X + 2. The 3X response to the Read-Rate Sample command in register 40301 is as follows.

In modules prior to V02.00, when Rate Sample mode was selected, input was always handled as if it were generated by a pulse encoder. For example, 60 count per revolution encoders, either pulse or quadrature types, would give a rate of 60 for a one-second revolution when the interval was set for one second.

The result is four times the rate sample value as would be accumulated with an equivalent pulse encoder input. In the example in the above paragraph, the rate sample would be equal to 240.

Encoder type selection is set using Command 1, CONFIGURE (01XX), 4X+1 register, bits 9 or 10 (see the description of Command 1 in this section).

If the Encoder Type select bits are set to 0, either type of encoder will produce the Rate Sample, as did versions of the module that were lower than V02.00.