Defined Architecture: Junctions
Original instructions
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Introduction
An M580 network can support both RIO modules (including BM•CRA312•0 X80 EIO adapter modules) and dual-ring switches (DRSs).
Both RIO modules and DRSs constitute a network junction, as follows:
Each junction presents the queueing point, which can add delay — or jitter — to the system. If two packets simultaneously arrive at a junction, only one can be immediately transmitted. The other waits for a period referred to as “one delay time” before it is transmitted.
Because RIO packets are granted priority by the M580 network, the longest an RIO packet can wait at a junction is one delay time before it is transmitted by the module or DRS.
The following scenarios depict how DRSs handle packets that arrive simultaneously.
DRS
In this example, a DRS receives a steady flow of packets from both the main ring and an RIO sub-ring:
The DRS handles RIO packets in this sequence:
Time
Ring In
Sub-ring
Ring Out
Comment
T0
1 (started)
a
–
Packet “a” arrived after transmission of packet “1” begins.
T1
2
b
1
Packets “2” and “b” arrive simultaneously.
T2
3
c
a
Packets “3” and “c” arrive simultaneously.
T3
4
d
2
Packets “4” and “d” arrive simultaneously.
T4
5
e
b
Packets “5” and “e” arrive simultaneously.
DRS with Sub-ring Cable Break
In this example, a DRS receives a steady flow of packets from the main ring and also from both segments of an RIO sub-ring with a cable break:
The DRS handles RIO packets in this sequence:
Time
Ring In
Sub-ring A
Sub-ring B
Ring Out
Comment
T0
1 (started)
a
p
–
Packets “a” and “p” arrive after transmission of packet “1” begins.
T1
2
b
q
1
Packets “2” , “b,” and “q” arrive simultaneously.
T2
3
c
r
a
Packets “3”, “c,” and “r” arrive simultaneously.
T3
4
d
s
p
Packets “4”, “d,” and “s” arrive simultaneously.
T4
5
e
t
2
Packets “5”, “e,” and “t” arrive simultaneously.