MAST Task Cycle Time: Internal Processing on Input and Output

General

The internal processing time for inputs and outputs is the sum of the following:

MAST task system overhead time
maximum communication system reception time and input management time for implicit inputs/outputs
maximum communication system transmission time and output management time for implicit inputs/outputs

MAST Task System Overhead Time

For BMX P34 2000/2010/20102/2020/2030/20302 processors, the MAST task system overhead time is 700 μs.

NOTE:

Three system words give information on the MAST task system overhead times:

%SW27: last cycle overhead time,
%SW28: longest overhead time,
%SW29: shortest overhead time.

Implicit Input/Output Management Time

The implicit input management time is the sum of the following:

Fixed base of 25 μs,
Sum of the input management times for each module (in the following table, IN).

The implicit output management time is the sum of the following:

Fixed base of 25 μs (FAST), 73 μs (MAST),
Sum of the output management times for each module (in the following table, OUT).

The table below shows the input (IN) and output (OUT) management times for each module.

Type of Module	Input Management Time (IN)	Output Management Time (OUT)	Total Management Time (IN+OUT)
BMX DDI 1602, 16 discrete inputs module	60 μs	40 μs	100 μs
BMX DDI 1603, 16 discrete inputs module	60 μs	40 μs	100 μs
BMX DDI 1604, 16 discrete inputs module	60 μs	40 μs	100 μs
BMX DDI 3202 K, 32 discrete inputs module	67 μs	44 μs	111 μs
BMX DDI 6402 K, 64 discrete inputs module	87 μs	63 μs	150 μs
BMX DDO 1602, 16 discrete outputs module	60 μs	45 μs	105 μs
BMX DDO 1612, 16 discrete outputs module	60 μs	45 μs	105 μs
BMX DDO 3202 K, 32 discrete outputs module	67 μs	51 μs	118 μs
BMX DDO 6402 K, 64 discrete outputs module	87 μs	75 μs	162 μs
BMX DDM 16022, 8 discrete inputs and 8 discrete outputs module	68 μs	59 μs	127 μs
BMX DDM 3202 K, 16 discrete inputs and 16 discrete outputs module	75 μs	63 μs	138 μs
BMX DDM 16025, 8 discrete inputs and 8 discrete outputs module	68 μs	59 μs	127 μs
BMX DAI 0805, 8 discrete inputs module	60 μs	40 μs	100 μs
BMX DAI 0814, 8 discrete inputs module	TBC	TBC	TBC
BMX DAI 1602, 16 discrete inputs module	60 μs	40 μs	100 μs
BMX DAI 1603, 16 discrete inputs module	60 μs	40 μs	100 μs
BMX DAI 1604, 16 discrete inputs module	60 μs	40 μs	100 μs
BMX DAI 1614, 16 discrete inputs module	TBC	TBC	TBC
BMX DAI 1615, 16 discrete inputs module	TBC	TBC	TBC
BMX DAO 1605, 16 discrete outputs module	60 μs	45 μs	105 μs
BMX DAO 1615, 16 discrete outputs module	TBC	TBC	TBC
BMX AMI 0410 analog module	103 μs	69 μs	172 μs
BMX AMI 0800 analog module	103 μs	69 μs	172 μs
BMX AMI 0810 analog module	103 μs	69 μs	172 μs
BMX AMO 0210 analog module	65 μs	47 μs	112 μs
BMX AMO 0410 analog module	65 μs	47 μs	112 μs
BMX AMO 0802 analog module	110 μs	110 μs	220 μs
BMX AMM 0600 analog module	115 μs	88 μs	203 μs
BMX ART 0414 analog module	103 μs	69 μs	172 μs
BMX ART 0814 analog module	138 μs	104 μs	242 μs
BMX DRA 1605, 16 discrete outputs module	60 μs	45 μs	105 μs
BMX DRA 0804, 8 discrete outputs module	56 μs	43 μs	99 μs
BMX DRA 0805, 8 discrete outputs module	56 μs	43 μs	99 μs
BMX DRA 0815, 8 discrete outputs module	TBC	TBC	TBC
BMX DRC 0805, 8 discrete outputs module	TBC	TBC	TBC
BMX EHC 0200 dual-channel counting module	102 μs	93 μs	195 μs
BMX EHC 0800 eight-channel counting module	228 μs	282 μs	510 μs

Communication System Time

Communication (excluding telegrams) is managed during the MAST task internal processing phases:

on input for receiving messages
on output for sending messages

The MAST task cycle time is, therefore, affected by the communication traffic. The communication time spent per cycle varies considerably, based on the following elements:

traffic generated by the processor: number of communication EFs active simultaneously
traffic generated by other devices to the processor, or for which the processor ensures the routing function as master

This time is only spent in the cycles where there is a new message to be managed.

NOTE: These times may not all occur in the same cycle. Messages are sent in the same PLC cycle as instruction execution when communication traffic is low. However, responses are never received in the same cycle as instruction execution.