MAST Task Cycle Time: Input/Output Internal Processing
(Original Document)
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Definition of Input and Output Internal Processing Time (Ipt)
Ipt = MAST task overhead system time (Most)
+ max [receiving communication system Time (rcomT); management time on input of implicit I/O %I (mTi%I)]
+ [sending communication system Time (scomT); management time on output of implicit I/O %Q (mTo%Q)]
MAST Task Overhead System Time (Most)
Summary table:
Processors
Time without Fipio application
Time with Fipio application
TSX 57 0244
1 ms
-
TSX 57 104
1 ms
-
TSX 57 1634
1 ms
-
TSX 57 154
1 ms
(1)
TSX P57 204
TSX PCI 57 204
1 ms
-
TSX P57 254
1 ms
(1)
TSX P57 2634
1 ms
-
TSX P57 304
1 ms
-
TSX P57 354
TSX PCI 57 354
TSX P57 3634
1 ms
(1)
(1)
-
TSX P57 454
TSX P57 4634
TSX H57 24M/44M
1 ms
(1)
-
-
TSX P57 554
1 ms
(1)
TSX P57 5634/6634
1 ms
-
(1) information available in Control Expert.
NOTE: Information is also available in Unity Pro version later than V2.0 (Unity Pro is the old name of Control Expert for versions ≤ V13.1).
Management Time on Input/Output of Implicit I/O %I and %Q
mTi%I = 60 micro seconds + sum of the IN times of each module.
mTo%Q = 60 micro seconds + sum of the OUT times of each module.
Management time on input (IN) and on output (OUT) for each module:
Module type
Management time
On input (IN)
On output (OUT)
Total (IN+OUT)
8 channel discrete inputs
27 μs
-
27 μs
16 channel discrete inputs
(all modules except TSX DEY 16FK)
27 μs
-
27 μs
32 channel discrete inputs
48 μs
-
48 μs
64 channel discrete inputs
96 μs
-
96 μs
Fast discrete inputs (8 channels used)
(TSX DEY 16FK/TSXDMY 28FK module)
29 μs
16 μs
45 μs
Fast discrete inputs (16 channels used)
(TSX DEY 16FK/TSXDMY 28FK/28RFK module)
37 μs
22 μs
59 μs
8 channel discrete outputs
26 μs
15 μs
41 μs
16 channel discrete outputs
33 μs
20 μs
53 μs
32 channel discrete outputs
47 μs
30 μs
77 μs
64 channel discrete outputs
94 μs
60 μs
154 μs
Analog inputs (in groups of 4 channels)
84 μs
-
84 μs
Analog outputs (4 channels)
59 μs
59 μs
118 μs
Counting (TSX CTY 2A/4A), by channel
55 μs
20 μs
75 μs
Counting (TSX CTY 2C), by channel
65 μs
21 μs
86 μs
Step by step control (TSX CFY ..), by channel
75 μs
20 μs
95 μs
Axis control (TSX CAY ..), by channel
85 μs
22 μs
107 μs
NOTE: Discrete input/output module times are given based on the assumption that all channels of the module are assigned to the same task.
Example: Using a TSX DEY 32 D2 K module
  • If the 32 channels are assigned to the same task, use the "32 channel discrete inputs" time,
  • If only 16 channels are assigned to the same task, use the "16 channel discrete inputs" time and not the "32 channel discrete input" time divided by 2.
Communication System Time
Communication (except telegram) is made during MAST task "Internal Processing" phases:
The MAST task cycle time is therefore affected by communication traffic. Communication time through each cycle varies considerably according to:
This time only applies in the cycles where there is a new message to be managed.
Send/receive time:
Processors
Send/receive time (1)
TSX P57 0244/104/1634/154
2 ms
TSX P57 204/254/2634
TSX PCI 57 204
1.5 ms
TSX P57 304/354/3634
TSX PCI 57 354
TSX P57 454/4634
TSX H57 24M/44M
1.5 ms
1.5 ms
0.6 ms
0.6 ms
TSX 57 554/5634/6634
0.4 ms
(1) including processing by the protocol drivers.
NOTE: These times cannot be combined in the same cycle. Transmission occurs in the same cycle as instruction execution as long as communication traffic remains light, but the reply is not received in the same cycle.
Example with terminal (with programming software) connected and animation table open
Processors
Average time per cycle
Maximum time per cycle
TSX P57 0244/104/1634/154
2 ms
3 ms
TSX P57 204/254/2634
TSX PCI 57 204
2 ms
3 ms
TSX P57 304/354/3634
TSX PCI 57 354
TSX P57 454/4634
TSX H57 24M/44M
2 ms
2 ms
1 ms
3 ms
3 ms
1.5 ms
TSX P57 554/5634/6634
0.6 ms
1 ms