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TSX P57 554 processors
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(Original Document)
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TSX P57 554 processors
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(Original Document)
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Characteristics
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TSX P57 554
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Maximum configuration
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Maximum number of TSX RKY 12EX racks
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8
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Maximum number of TSX RKY 4EX/6EX/8EX racks
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16
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Maximum number of slots
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111
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Maximum number of simultaneous communication EF
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80
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Functions
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Maximum number of channels
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In-rack discrete I/O
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2048
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In-rack analog I/O
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512
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Application
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64
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Maximum number of connections
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Built-in Uni-Telway (terminal port)
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1
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Network (ETHWAY, Fipway, Modbus Plus)
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4
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Master Fipio (built-in): No. of devices
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127
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Third party field bus
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5
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AS-i field bus
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8
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Savable real-time clock
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yes
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Process control channels
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30
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Process control loops
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90
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Memory
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Savable internal RAM
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1024K8 (1)
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PCMCIA memory card (maximum capacity)
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7168K8
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Application structure
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Master task
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1
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Fast task
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1
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Auxiliary task
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4
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Event processing (1 has priority)
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128
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Application code execution speed
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Internal RAM
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100% Boolean
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19.80 Kins/ms (2)
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65% Boolean + 35% digital
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14.20 Kins/ms (2)
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PCMCIA card
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100% Boolean
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19.80 Kins/ms (2)
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65% Boolean + 35% digital
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14.20 Kins/ms (2)
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Execution time
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Basic Boolean instruction
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0.0375/0.045 μs
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Basic digital instruction
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0.045/0.06 μs
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Floating point instruction
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0.48/0.56 μs
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System overhead
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Master task
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1 ms
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Fast task
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0.07ms
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