MAST Task Cycle Time: Internal Processing on Input and Output

General

The internal processing time for inputs and outputs is the sum of the following:

MAST task system overhead time
maximum communication system reception time and input management time for implicit inputs/outputs
maximum communication system transmission time and output management time for implicit inputs/outputs

MAST Task System Overhead Time

For BMEP58•0•0 processors, the MAST task system overhead time is 700 μs.

NOTE: Three system words give information on the MAST task system overhead times:

%SW27: last cycle overhead time
%SW28: longest overhead time
%SW29: shortest overhead time

Implicit Input/Output Management Time

The implicit input management time is the sum of the following:

Fixed base of 25 μs
Sum of the input management times for each module (in the following table, IN)

The implicit output management time is the sum of the following:

Fixed base of 25 μs (FAST), 73 μs (MAST)
Sum of the output management times for each module (in the following table, OUT)

The table below shows the input (IN) and output (OUT) topological (T) and DDT (DDT) management times for each module.

T	Module	Input Management Time (IN) ( μs)	Output Management Time (OUT) ( μs)	Total Management Time (IN+OUT) ( μs)
DDT	Module	Input Management Time (IN) ( μs)	Output Management Time (OUT) ( μs)	Total Management Time (IN+OUT) ( μs)
T	BMXDDI1602, 16 discrete inputs module	60	40	100
DDT	BMXDDI1602, 16 discrete inputs module	30	29	60
T	BMXDDI3202K, 32 discrete inputs module	67	44	111
DDT	BMXDDI3202K, 32 discrete inputs module	34	31	64
T	BMXDDI6402K, 64 discrete inputs module	87	63	150
DDT	BMXDDI6402K, 64 discrete inputs module	40	43	83
T	BMXDDO1602, 16 discrete outputs module	60	45	105
DDT	BMXDDO1602, 16 discrete outputs module	31	34	64
T	BMXDDO1612, 16 discrete outputs module	60	45	105
DDT	BMXDDO1612, 16 discrete outputs module	30	33	63
T	BMXDDO3202K, 32 discrete outputs module	67μs	51μs	118
DDT	BMXDDO3202K, 32 discrete outputs module	33	35	69
T	BMXDDO6402K, 64 discrete outputs module	87	75	162
DDT	BMXDDO6402K, 64 discrete outputs module	40	50	89
T	BMXDDM16022, 8 discrete inputs and 8 discrete outputs module	68	59	127
DDT		44	51	95
T	BMXDDM3202K, 16 discrete inputs and 16 discrete outputs module	75	63	138
DDT		48	54	102
T	BMXDDM16025, 8 discrete inputs and 8 discrete outputs module	68	59	127
DDT		44	51	95
T	BMXDAI0805, 8 discrete inputs module	60	40	100
DDT	BMXDAI0805, 8 discrete inputs module	28	28	56
T	BMXDAI1602, 16 discrete inputs module	60	40	100
DDT	BMXDAI1602, 16 discrete inputs module	29	29	59
T	BMXDAI1603, 16 discrete inputs module	60	40	100
DDT	BMXDAI1603, 16 discrete inputs module	30	29	59
T	BMXDAI1604, 16 discrete inputs module	60	40	100
DDT	BMXDAI1604, 16 discrete inputs module	30	29	58
T	BMXDAO1605, 16 discrete outputs module	60	45	105
DDT	BMXDAO1605, 16 discrete outputs module	30	33	64
T	BMXAMI0410 analog module	103	69	172
DDT	BMXAMI0410 analog module	43	42	85
T	BMXAMI0800 analog module	103	69	172
DDT	BMXAMI0800 analog module	63	65	129
T	BMXAMI0810 analog module	103	69	172
DDT	BMXAMI0810 analog module	63	65	128
T	BMXAMO0210 analog module	65	47	112
DDT	BMXAMO0210 analog module	30	35	65
T	BMXAMO802 analog module	110	110	220
DDT	BMXAMO802 analog module	47	74	121
T	BMXAMM0600 analog module	115	88	203
DDT	BMXAMM0600 analog module	82	80	162
T	BMXDRA0804, 8 discrete outputs module	56	43	99
DDT	BMXDRA0804, 8 discrete outputs module	27	31	58
T	BMXDRA0805, 8 discrete outputs module	56	43	99
DDT	BMXDRA0805, 8 discrete outputs module	28	31	59
T	BMXEHC0200 dual-channel counting module	102	93	195
DDT	BMXEHC0200 dual-channel counting module	101	108	208
T	BMXEHC0800 eight-channel counting module	228	282	510
DDT	BMXEHC0800 eight-channel counting module	261	317	578

Communication System Time

Communication (excluding telegrams) is managed during the MAST task internal processing phases:

on input for receiving messages
on output for sending messages

The MAST task cycle time is, therefore, affected by the communication traffic. The communication time spent per cycle varies considerably, based on the following elements:

traffic generated by the processor: number of communication EFs active simultaneously
traffic generated by other devices to the processor, or for which the processor ensures the routing function as master

This time is only spent in the cycles where there is a new message to be managed.

NOTE: These times may not all occur in the same cycle. Messages are sent in the same PLC cycle as instruction execution when communication traffic is low. However, responses are never received in the same cycle as instruction execution.