Modules TSX DEY 16FK and TSX DMY 28FK are equipped with the input latching function.
The input latching function allows particularly short pulses with a duration lower than the PLC cycle time to be taken into account.
This function takes the pulse into account, in order to process it in the following master (MAST) or fast (FAST) task cycle without interrupting the PLC cycle.
The pulse is taken into account when the input’s status is changed, which can be either:
-
a switch from 0 to 1
;
-
a switch from 1 to 0
.
The following diagram shows the process of latching a state on a pulse from 0 to 1.
The following diagram shows the process of latching a state on a pulse from 1 to 0.
The following table gives a description of the elements shown in the above diagrams:
|
Reference Number
|
Description
|
|
I
|
Input acquisition.
|
|
A
|
Processing of program.
|
|
S
|
Outputs updated.
|
NOTE: the time separating the arrival of two pulses at the same input must be greater than or equal to two PLC cycle times.
NOTE: the minimum duration of a pulse must be greater than the chosen filtering time.
