|
Address
|
Standard Symbol
|
Description
|
Counting mode concerned
|
|---|---|---|---|
|
%IWr.m.c.10.0
|
EVT_RUN
|
Event due to start of counting.
|
One Shot Counter mode
|
|
%IWr.m.c.10.1
|
EVT_MODULO
|
Event due to counter being equal to modulo value - 1 or equal to value 0.
|
|
|
%IWr.m.c.10.2
|
EVT_SYNC_PRESET
|
Event due to a synchronization or counter homing.
|
|
|
%IWr.m.c.10.3
|
EVT_COUNTER_LOW
|
Event due to counter being less than the lower threshold.
|
|
|
%IWr.m.c.10.4
|
EVT_COUNTER_WINDOW
|
Event due to counter being between the upper and lower thresholds.
|
|
|
%IWr.m.c.10.5
|
EVT_COUNTER_HIGH
|
Event due to counter being greater than the upper threshold.
|
|
|
%IWr.m.c.10.6
|
EVT_CAPT_0
|
Event due to capture 0.
|
|
|
%IWr.m.c.10.7
|
EVT_CAPT_1
|
Event due to capture 1.
|
Free Large Counter mode
|
|
%IWr.m.c.10.8
|
EVT_OVERRUN
|
Event due to overrun
|
|
|
Address
|
Description
|
|---|---|
|
%QWr.m.c.1.0
|
Start of counting event validation bit.
|
|
%QWr.m.c.1.1
|
Counter rollovering modulo, 0 or its limits event validation bit.
|
|
%QWr.m.c.1.2
|
Synchronization or counter homing event validation bit.
|
|
%QWr.m.c.1.3
|
Counter less than lower threshold event validation bit.
|
|
%QWr.m.c.1.4
|
Counter between the upper and lower thresholds event validation bit.
|
|
%QWr.m.c.1.5
|
Counter greater than upper threshold event validation bit.
|
|
%QWr.m.c.1.6
|
Capture 0 event validation bit.
|
|
%QWr.m.c.1.7
|
Capture 1 event validation bit.
|